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altera_lwip
- 已移植到altera nios ii软核的基于microC/OS操作系统的lwip全套源代码- Transplanted to altera the nios ii soft nucleus based on microC/OS the operating system lwip complete set source code
SIN_fashengqi
- 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（
adda_spi
- 这个源码是用altera公司的开发工具NIOS II IDE开发的基于软核处理器的AD、DA控制程序，通过spi 核控制AD、DA的时序，实现正弦波发送和接收-this source is altera company development tools NIOS II IDE - based soft-core Office JIMMY of AD and DA control procedures, spi nuclear control AD and DA timetables to ac
three_wave
- 此源码是利用altera公司的NIOS II IDE开发的，功能是通过spi 核控制AD/DA发三角波-this source is the use of altera NIOS II IDE. function through spi nuclear control AD / DA fat triangular wave
buttonpio
- 此源码是利用altera公司的nios II IDE开发的，主要功能是利用中断实现按钮响应
tut_DE2_sdram_vhdl
- This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
niox
- Open source and clean clone of Altera NIOS-II Soft Processor. Not completed but some test do run ok.
Lab2a
- C Code for a Nios II to switch led on a board with an FPGA ALTERA
FFTVHDl
- 基于FPGA的fft实现 摘要：本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核，代替传统DSP芯片或高性能单片机，实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core
DE2_NIOS_HOST_MOUSE_VGA
- 在ALTERA的DE2开发板上做的关于HOST_MOUSE的例子，基于Quartus II 和SOPC Builder以及Nios II IDE平台所完成！-ALTERA development in the DE2 board to do on HOST_MOUSE example, based on the Quartus II and SOPC Builder and Nios II IDE platform completed!
Altera_Proj
- altera nios ii ide c code
IICbus
- 基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02
DDR SDRAM Design Tutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
PaintBrush
- To use the device port ISP1362 and NIOS II CPU for mouse movement detection and the VGA interface and implement a Paint Brush Application[1] using Cyclone II FPGA on the Altera DE2 board.
High-Speed-FFT
- 优秀硕士论文，课题采用现场可编程门阵列((FPGA)，设计实现了一种超高速FFT处理器。目前，使用FPGA实现FFT多采用基2和基4结构，随着FPGA规模的不断扩大，使采用更高基数实现FFT变换成为可能。本课题就是采用Alter的Stratix II芯片完成了基16-FFT处理器的设计。在设计实现过程中，以基2-FFT搭建基16-FFT的运算核，合理安排时序，解决了碟形运算、数据传输和存储操作协调一致的问题。由于采用流水线工作方式，使整个系统的数据交换和处理速度得以很大提高。本设计实现了4096
DE2_NIOS_DEVICE_LED
- Altera DE2基于nios 软核的片子的led 驱动-This designs uses a Nios II system to demonstrate how to communicate with the DE2 board via the USB device connection. The software on the PC communicates with the DE2 board to tell it to increment an internal counter. T
altera_avalon_uart
- Altera NIOS II uart 驱动-uart driver in NIOS II
dma
- Altera NIOS II DMA 驱动-Altera NIOS II DMA driver
1211794911-altera-video-surveillance
- altra nios II video system
niosii-triple-speed-ethernet-4sgx230-qsys-131
- Altera公司出的三速以太网例程，工程编译完了可以用niosii直接生成simple_socket_server，希望有用。(Altera company out of the three speed Ethernet routines, engineering finished, you can directly generate simple_socket_server using NiosII, I hope useful.)